THE M8051 AND M8052

LIKE THE INTEL 87C51 AND 87C52, THESE DESIGNS USE A TWELVE CLOCK MACHINE CYCLE, FEATURING TWO MEMORY ACCESSES IN EACH MACHINE CYCLE.

Instructions typically take either twelve or twenty-four clock cycles to execute. Only the multiply and divide instructions take longer, consuming 48 clock cycles.

By modern standards, this instruction rate appears low. However when a design is required as a drop in replacement for a discrete 8051, these designs tend to be easier to adopt than optimised 8051 implementations. Preservation of the precise clock-to-instruction ratio is often a requirement where existing software relies on timing relationships with peripheral devices such as interrupts, counters and timers etc.

As the simplest designs in the portfolio, these are the most competitively priced.

The M8052 is similar to the M8051, and includes an additional 16-bit counter timer and has the capacity to address 256 bytes of register memory.

DOWNLOAD THE M8051 DATASHEET HERE

DOWNLOAD THE M8052 DATASHEET HERE