PRODUCT LICENCES

ALL OUR DESIGNS ARE DELIVERED AS SYNTHESISABLE RTL SOURCE CODE IN BOTH VHDL '93 AND VERILOG 2001 LANGUAGES.

INCLUDED WITH THE RTL ARE THE FOLLOWING STANDARD DELIVERABLES:

• A configuration script to help you customise the design source to your particular requirements.
• A self-checking testbench simulation environment that demonstrates all of the design functionality using behavioural HDL, and an assembler code test program. This testbench can be used to check out your RTL and netlist implementations of the product.
• Example Modelsim and Cadence simulation scripts.
• Example Synopsys, Xilinx and Quartus constraint and synthesis scripts.
• Example scan insertion scripts for Synopsys and Mentor tools.
• Comprehensive documentation including a concise product specification and a practical user guide contain implementation guidance and examples.

LICENSING MODEL

All our products are provided by way of a royalty-free end user licence agreement (EULA). You can choose to take a single use licence, or a multiple-use “buyout” licence for use in an unlimited number of projects. The single use licence entitles you to use the deliverables in a single design project, comprising a single mask production and any shrinks and bug-fixing re-spins of the same design. Each new EULA includes a twelve month support agreement. Click here for more information on support.